In order to minimize the space required by display devices, research into the development of various flat panel display devices such as LCD display devices, plasma display panels (PDP) and electro-luminescence displays (EL), has been undertaken to displace larger cathode-ray tube displays (CRT) as the most commonly used display devices. Particularly, in the case of LCD display devices, liquid crystal technology has been explored because the optical characteristics of liquid crystal material can be controlled in response to changes in electric fields applied thereto.
At present, the dominant methods for fabricating liquid crystal display devices (LCD) and panels are methods based on amorphous silicon (a-Si) thin film transistor (TFT) technologies. Using these technologies, high quality image displays of substantial size can be fabricated using low temperature processes. As will be understood by those skilled in the art, conventional LCD devices typically include a transparent (e.g., glass) substrate with an array of thin film transistors thereon, pixel electrodes, orthogonal gate and data lines, a color filter substrate and liquid crystal material between the transparent substrate and color filter substrate. The use of a-Si TFT technology typically also requires the use of separate peripheral integrated circuitry to drive the gates and sources (i.e., data inputs) of the TFTs in the array. Therefore, there is typically provided a large number of pads for connecting the gate lines (which are coupled to the gates of the TFTs) and data lines (which are coupled to the sources of the TFTs) to the peripheral drive circuitry.
Unfortunately, a-Si TFT devices may be prone to relatively large off-state leakage currents in part because amorphous silicon typically has a relatively high photoconductivity. One attempt to reduce leakage currents included the use of thinner amorphous silicon active regions having higher net source-to-drain resistance. However, these thinner active regions are typically susceptible to deterioration when these regions are exposed to back-end processing steps which include chemical etchants, for example. To address this problem, methods have been proposed to reduce the likelihood that thinner active regions will be adversely affected by back-end processing steps.
For example, FIG. 1 illustrates a prior art TFT display device which includes a protective etch-stop region and FIGS. 2A-2D illustrate a method of fabricating the device of FIG. 1. In particular, FIG. 1 illustrates a TFT display device comprising a gate electrode 2 on a substrate 1, a gate insulating region 3 on the gate electrode and a patterned amorphous silicon region 4 on the gate insulating region 3, opposite the gate electrode 2. A relatively highly doped amorphous silicon contact region 4 is also provided to facilitate the formation of low resistance contacts between source and drain electrodes 7 and 8 and the patterned amorphous silicon region 4. An etch stop 5 is also provided so that during a step of patterning the amorphous silicon contact region 4 into separate regions, the channel portion of the patterned amorphous silicon region 4 is not exposed to a chemical etchant. The TFT display device is also protected by a passivation layer 9. A conventional method of forming the TFT display device of FIG. 1 will now be described. As illustrated best by FIG. 2A, a gate electrode 2 is initially patterned on a face of a transparent substrate 1 and then a blanket electrically insulating layer 3 is deposited on the gate electrode 2. Then, a blanket amorphous silicon layer 40 and nitride layer 50 are formed in sequence on the electrically insulating layer 3 using such conventional techniques as plasma enhanced chemical vapor deposition (PECVD).
Referring now to FIG. 2B, a layer of photoresist (not shown) is then deposited on the nitride layer 50 and exposed by a light source which penetrates the substrate 1, but is selectively blocked by the patterned gate electrode 2. An etch stopper 5 is then formed by wet etching the nitride layer 50 using the layer of photoresist as a mask. As illustrated best by FIG. 2C, a doped layer of amorphous silicon (e.g. N-type) is deposited on the etch stopper 5 and on the blanket amorphous silicon layer 40. The doped layer of amorphous silicon and blanket amorphous silicon layer 40 are then patterned using conventional techniques to define an amorphous silicon active region 4 having a doped amorphous silicon contact region 6 thereon. Referring now to FIG. 2D, a blanket metal layer is then deposited and patterned using an etching technique to define source and drain electrodes 7 and 8. Here, during the step of patterning the blanket metal layer, the doped amorphous silicon contact region 6 is also etched to form separate source and drain amorphous silicon contact regions. During this patterning step, the etch stopper 5 is used as a mask to protect the amorphous silicon active region 4 from etching damage. Thereafter, a blanket passivation layer is formed on an upper surface of the TFT device.
Notwithstanding the above described method of forming TFT display devices, there continues to be a need for improved methods of forming TFT display devices.